About Architect

Architect is building the intelligence layer for chip companies to bring the time to tapeout from 3 years to 6 months. Our AI amplifies your hardware engineers across DI, DV, and PD workflows, help build IP from the ground up, and keeps you in the loop at every step.

Founded out of Stanford, we’re one of the fastest-moving Bay Area startups, blending frontier ML with deep chip design expertise to transform a trillion-dollar industry. Backed by top VCs and legendary angels, we’re assembling a world-class team of founding engineers and researchers to architect the next era of silicon.

What You’ll Do

• Lead RTL design and verification efforts that directly impact our AI-driven chip design platform
• Take ownership of hardware evaluation frameworks and drive benchmarking initiatives
• Work closely with ML engineers to translate hardware requirements into actionable specifications
• Build and maintain hardware testing infrastructure that validates our AI-generated designs
• Lead client conversations to understand hardware requirements and translate them for the technical team
• Architect and implement hardware evaluation pipelines from requirements gathering to validation

What We’d Like to See

• Degree: BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• Chip-team experience: At least one role on a chip-design or tape-out team (e.g., NVIDIA, Synopsys, Cadence); for founding engineers, a minimum of 2 years in industry is required (4 years+ strongly preferred).

• Coding skill: Python & Bash power user—comfortable writing scripts, data pipelines, or CI/CD around EDA flows

• EDA proficiency: Hands-on with standard Synopsys/Cadence tools (Xcelium, Genus, Innovus, etc.) and associated TCL flows

• Specialty (pick one):
• • Design Integration/RTL/Architecture: Built RTL in SystemVerilog for complex IP blocks
  • Design Verification: Strong UVM/SystemVerilog verification methodology experience
  • Physical Design: Led synthesis, floorplanning, P&R, timing, or physical verification on leading-node tape-outs

• Bonus:
• • Prior work on AI-for-chip-design teams (e.g., Synopsys, Cadence, NVIDIA ML workflows) or DFT/power-optimization flow experience
  • Methodology/Flow experience, having built production systems that manage flow and handoff across several stages of design.

What We Offer

• Competitive salary and meaningful equity stake
• Fast-paced startup with autonomy and visible impact
• Cutting-edge AI-driven chip design challenges