About Eridu AI 

Eridu AI is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate training and inference for large-scale AI models. Today’s AI performance is frequently limited by system-level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors, software, and systems to unlock greater GPU utilization, reduce capital and power costs, and maximize data center efficiency. The company’s solutions and value proposition have been validated by several leading hyperscalers.

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED company and developer of the first augmented reality contact lens).

Position Overview

We are seeking a Synthesis Engineer to help define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. 

Responsibilities 

• Define and maintain the synthesis flow—including logic and physical synthesis. 

• Develop and manage synthesis design constraints (e.g., SDC). 

• Design and architect top-level and block-level floorplans for multi-chiplet systems and interposers. 

• Collaborate with micro-architects on feasibility studies and performance, power, and area (PPA) tradeoffs. 

• Work with the Design and DFT teams on scan insertion and synthesis implementation steps. 

• Partner with Design Verification to support equivalence checking and functional sign-off. 

• Assist in defining and integrating low-power optimization strategies into the synthesis flow. 

Qualifications

• Master’s or Bachelor’s degree in Electrical Engineering. 

• Minimum 15+ years of relevant experience. 

• Prior experience with multiple tapeouts in deep sub-micron nodes (7nm or below) is required. 

• Proficiency with Cadence Innovus/Genus or Synopsys Fusion Compiler. 

• Strong scripting skills in Unix shell, Perl, Python, and TCL. 

• Deep understanding of CDC/RDC flows and equivalence checking. 

• Familiarity with CAD tools and logic/physical design principles for low-power, high-performance chips. 

• Knowledge of foundation libraries, VT tradeoffs, multi-track library usage, synchronizers, and lock-up latches. 

• Exposure to datapath synthesis, memory compilers, and power optimization. 

• Knowledge of Verilog and SystemVerilog. 

• Understanding of device physics and deep sub-micron technologies. 

• Experience with EMIB architectures and chip-to-chip bridging is a plus. 

• Strong problem-solving, communication, and organizational skills. 

• Ability to work effectively in fast-paced teams under aggressive development schedules. 

Why Join Us?

At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.  

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.