Validation Director

About Eridu AI 

Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI’s solution and value proposition have been widely validated with several hyperscalers.  

  

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED display company and developer of the first augmented reality contact lens).


Position Overview

We are seeking a Validation Director to lead the post-silicon validation and bring-up efforts for our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining validation strategy, overseeing global lab operations, and driving execution from silicon bring-up through productization across cutting-edge networking devices.


Responsibilities 

  • Global Team Leadership: Manage and lead a diverse, global team of post Silicon Validation engineers, fostering an inclusive and collaborative work environment. Ensure effective communication and coordination across different geographical locations.
  • Specialized post Silicon Validation Strategy: Develop and oversee the implementation of verification strategies for ASICs in the area of switch fabric, leveraging your extensive experience in networking,
  • Technical Expertise in post Silicon Validation and Bring up: Provide technical leadership in  design of bring up board and High Speed Serdes training and calibration.
  • Debug Capability: Lead issue triage and root-cause analysis for silicon-related failures, from lab environments to live systems. Use production telemetry and system-level data to drive improvements in silicon validation and influence future design iterations.
  • Firmware Collaboration: Work closely with Firmware teams to validate , ensuring seamless integration and functionality between hardware and firmware components.
  • System & Board Level Expertise:  Prior experience n contributing to bring up board design and Strong experience with IEEE protocols pertaining to IP testing.
  • Lab Expertise: Prior experience with High-speed Protocol Analyzers (e.g., PICe Gen6, Ethernet), PRBS, traffic generators.
  • Team Development: Mentor and develop team members, identifying training needs and opportunities for growth Prior experience with dealing with third party team augmentation in varied geographical locations.

Qualifications

  • Education: Master’s degree or higher in Electrical Engineering, Computer Engineering, or related field.
  • Experience: A 15-year Minimum in post Silicon Validation in the area of enterprise networking.
  • Technical Skills: Expertise in Hardware Validation, Chip Bring up ,  High Speed Serdes Training and Calibration.
  • Prior experience with Ethernet and PCIe Protocols and UCIe ( or D2D) protocols required.  System Debug experience a plus. Strong prior experience with CHiplets and Interposers a plus.
  • Leadership and Management Skills: Proven track record in managing and leading global teams. Excellent people management skills, including experience in cross-cultural team dynamics.
  • Communication Skills: Exceptional communication abilities, capable of effectively coordinating and leading a global team, and articulating complex technical issues in a clear manner.

Why Join Us?

At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.  

   

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

The pay range for this role is:

210,000 - 285,000 USD per year (san francisco bay area)

ASIC Engineering

Saratoga, CA

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