About Eridu AI 

Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI’s solution and value proposition have been widely validated with several hyperscalers.  

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED display company and developer of the first augmented reality contact lens).

Key Responsibilities

• Define chip power budgets of multiple ASIC chips and percolate into subsystem and block level budgets.
• Ability to do RTL level power analysis, and corelate code level and post PnR level power analysis.
• Good understanding of power delivery and power dissipation/cooling issues.
• Understanding of EM/IR drop issues, and mitigation.
• Guide RTL designers to utilize power saving techniques such as: self-enabling, self-clocking flops, bank registers, and activity based refactorization techniques to reduce power.
• Proficiency in Synthesis design constraints. (ie; SDC).
•  Sound Proficiency in PowerArtist, Power Compiler, Prime Power, and other RTL or gate level analysis tools.
• Prior exposure to UPF based power optimization techniques, and ability to do power-based gate level simulations.
• Work with Ips to enable good power performance tradeoffs.
• Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.

Qualifications

• Prior experience with power optimization of large designs.
• Ability to run SPICE on large clock trees to reconcile timing related issues.
• Knowledge using synthesis, place & route, analysis and verification CAD tools.
• Knowledge of Verilog/System Verilog required.
• Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
• Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL
• Good understanding of device physics and experience in deep sub-micron technologies 5nm or below.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Ability to work well in a team and be productive under aggressive schedules.
• Prior experience of multiple tape-out in deep submicron 7nm or below is required.
•  Master’s Degree or bachelor’s degree in EE with a minimum of 7+ years of experience.

Why Join Us? 

At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. 

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.