About Eridu AI  

Eridu AI is a Silicon Valley hardware startup revolutionizing AI training performance. Our innovative solutions address bottlenecks in data centers, enhancing GPU utilization, reducing training cycles, and lowering costs. Validated by AI market leaders, including hyperscalers and other large, well-known AI market participants, our technology is poised to unlock unparalleled AI performance. 

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, systems and software, including serial entrepreneur Drew Perkins, Co-Founder of Infinera (NASDAQ: INFN, Lightera (acquired by Ciena), Gainspeed (acquired by Nokia) and Mojo Vision (the world’s leading micro-LED display company and developer of the first augmented reality contact lens). 

Position Overview  

We are seeking an RTL Director/Senior Director to define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. 

Responsibilities: 

• Provide technical leadership and direction for the entire Chip RTL team. 
• Collaborate with Chip and System Architects to translate architecture requirements into microarchitecture and design implementation. 
• Work with customers and stakeholders to understand feature requirements and translate them into implementable specifications. 
• Perform RTL coding, code reviews, and debugging. 
• Document microarchitecture and RTL subsystems. 
• Set and enforce quality standards for RTL development. 
• Engage in post-silicon activities such as bring-up, platform validation, characterization, parameter optimization, and final productization. 
• Support the definition of development flows that improve efficiency and quality of execution. 
• Work closely with Physical Design, Firmware, and Design Verification teams to ensure successful end-to-end RTL implementation. 
• Leverage domain experience with Ethernet protocols to inform design decisions.  

Qualifications: 

• MSEE with at least 15+ years of experience. 
• Proven record of successful tape-outs and productization, preferably in networking devices. 
• Ability to translate architecture-level feature descriptions into implementable designs, including clear documentation for execution and verification. 
• Experience guiding teams at a technical level and working with external groups to understand requirements and devise workable solutions to inter-IP challenges. 
• Thorough understanding of multiple clock/reset/power domain design challenges and safe/robust design practices. 
• Experience in refactoring/restructuring designs to solve timing/area challenges, including algorithmic and structural design changes. 
• Expertise in optimizing hardware versus firmware implementation for overall product performance/efficiency. 
• Excellent knowledge of industry-standard tools and best-in-class practices for high-quality RTL development. 
• Prior experience in source synchronous design implementation. 
• Knowledge of networking protocols is essential. 
• Experience with micro-architectural specification of ASIC’s. 
• Good understanding of the ASIC design flow, including DFT and physical implementation requirements. 

Why Join Us? 

At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. 

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.