NPU Architect

SAPEON: We Make AI Happen

Our mission is to create cutting-edge technology that serves humanity. 
As an AI-focused semiconductor chip and systems developer, we continuously explore new and innovative ways to solve real-world problems. Our team is dedicated to pushing the boundaries of what is possible and passionate about making a real impact. 
With our flagship series of AI semiconductor chips, we deliver unparalleled performance and efficiency in machine learning and deep learning applications across various industries, including security, media, manufacturing, mobility, and automotive.
Join our journey to create a happier, more enriched humanity that can address today's challenges while making strides toward a greener future.

About the role

The NPU (Neural Processing Unit) Architect will be responsible for designing and optimizing Machine Learning accelerator architectures to improve performance, power, area, and flexibility for various neural networks in SAPEON’s X series chips. This role will require analyzing existing and emerging neural networks to identify bottlenecks and areas for innovation and applying innovative approaches to design and optimize NPUs.  The candidate should have a strong background in computer architecture and have performance modeling experience in at least one of the following: ML Accelerators, CPUs, GPUs.  He/she must be willing to expand their knowledge into other semiconductor areas such as process, memory, interconnect, and packaging.   An ideal team member is courageous when it comes to trying new things, is adept at reasoning about systems performance, and is willing to iterate to prove out ideas. 


The ideal candidate should also have experience in NPU micro-architecture, RTL coding, simulators, verification environments, operating systems, and ML compilers to help build up the entire system.

What you'll do

  • Defining new NPU architectures and optimize existing ones to improve performance/power/area metrics and flexibility for neural networks
  • Analyze existing and emerging neural networks to identify bottlenecks and opportunities for innovation
  • Use innovative approaches to improve NPU architecture while working cross-functionally across teams (RTL/DV/SW/ML Applications)
  • Assess feasibility of ideas, refine them and document them in High Level Architectural Specs


  • 5+ years of experience in hardware design at the architectural level in either NPU, CPU, GPU
  • Experience in PPA (power/performance/area) optimizations and proving those optimizations through paper analysis and through functional/performance hardware simulation
  • Programming skills in C/C++ and Python
  • Experience in hardware simulator development

Preferred qualifications
  • Experience in NPU, GPU, and micro-processor development; especially many-core and multi-chip systems
  • Experience with ML networks and ML frameworks (Tensorflow, PyTorch, TVM, and so on)
  • Experience in architecture exploration tool development
  • Possess experience in NPU micro-architecture, RTL, synthesis, verification, and Neural Network Compilers
  • Familiar with hardware description languages – Verilog/SystemVerilog for both design and verification
  • Exposure to Cuda/OpenCL or some other parallel programming language
  • Familiar with operating system concepts
  • Familiar with process technology, memory, on-chip and inter-chip interconnect, dynamic-voltage-and-frequency (DVFS) scaling and packaging technology

  • Competitive compensation + equity plan 
  • Medical/Dental/Vision/Life Insurance with no premium cost
  • Retirement plan with company matching
  • PTO and paid holidays

The pay range for this role is:

200,000 - 250,000 USD per year (SAPEON HQ)


Santa Clara, CA

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