The Role

As Power Architecture Lead for PMIC, you will own the IVR architecture end-to-end — power conversion topology, digital control engine and analog subsystems. You will work directly with the Head of Engineering, digital architecture leads, and analog design team, and engage foundry partners and key customers at the architecture level.

This role requires equal fluency in power electronics and mixed-signal IC design. You will define the architecture, validate the tradeoffs across topology, packaging, and thermal constraints, and drive execution through tape-out.

Key Responsibilities

Architecture & Definition

•     Define IVR architecture: multi-phase interleaved buck converter topology, phase count configurability, switching frequency selection, and efficiency targets across load conditions

•     Architect the digital control engine: per-phase duty cycle control, current balance, DVFS sequencing, and transient response optimization for AI workload dynamics

•     Define the control and telemetry interface

•     Establish power domain architecture for multi-domain compute targets: phase allocation, rail sequencing, and cross-domain coordination

•     Define input power spec, inrush management, and integration requirements for in-package passive components including integrated inductors

Mixed-Signal & Analog Oversight

•     Define requirements for analog subsystems: gate drivers, current sensing (DCR / integrated sense), on-chip thermal diodes, and oscillator / clock generation

•     Oversee integrated inductor evaluation and selection — saturation current, DCR, Q-factor, and co-design with converter switching frequency

•     Establish PVT corner strategy and margin targets across process, voltage, and temperature for all analog blocks

•     Drive analog-digital co-design: ensure digital control loop stability across all PVT corners with defined phase margin and gain margin targets

•     Define ESD and latch-up protection strategy for high-current power bumps

Implementation Oversight

•     Guide process node selection for Gen 1 and roadmap generations — evaluate tradeoffs between power density, analog capability, and cost

•     Lead IP evaluation for gate driver, ADC, and reference blocks; define custom vs. licensed IP strategy

•     Drive DFT strategy for power chiplet: stuck-at fault coverage, analog BIST for converter calibration, and production test requirements

•     Define packaging integration requirements

Customer & Ecosystem Engagement

•     Translate AI compute platform power delivery requirements into product specifications — engage customers at the architecture level to validate rail counts, current targets, and transient profiles

•     Interface with foundry partners on process capability, passive integration options, and packaging design rules

•     Support technical due diligence for strategic partnerships and customer evaluations

Roadmap & IP

•     Define the multi-generation architecture roadmap — establish a clear migration path from initial process node to advanced nodes with improved power density and packaging integration

Required Qualifications

•     15+ years in power IC architecture; 5+ years at Principal level or higher in a fabless, IDM, or PMIC-focused semiconductor environment

•     Deep expertise in multi-phase synchronous buck converter design — topology selection, loop compensation, stability analysis, and efficiency optimization across load

•     Mixed-signal IC design fluency: gate driver design, current sensing techniques, analog control loops, and ADC/DAC integration in CMOS processes

•     Hands-on experience with integrated passive components — on-chip or in-package inductors, capacitors, and their interaction with converter performance

•     Advanced packaging familiarity: flip-chip, 2.5D/3D integration, bump map design, and thermal/electrical co-design for power-dense applications

•     Experience driving power IC tape-outs from architecture definition through silicon bring-up and characterization

•     Proficiency in power converter simulation: SPICE-level transient analysis, AC loop stability, and PVT corner sweeps

Preferred Qualifications

•     Experience with kilowatt-class power delivery for AI accelerators, GPUs, or high-performance CPUs is a big plus

•     Familiarity with in-package voltage regulator architectures (FIVR, LEGO-style VR, or substrate-embedded passives)

•     Background in PMBus / I2C / proprietary digital power management interfaces — experience migrating from legacy interfaces to die-to-die control fabric is a plus

•     Prior startup experience or comfort with early-stage technical ambiguity and fast-paced execution

About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

•       Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

•       Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

•       IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

•       If you have an idea, we test it. If it works, we ship it.

•       No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

•       US team: Bay Area preferred, but we hire the best people regardless of location

•       India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

•       Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.

•       Bias for action. We move fast. Analysis paralysis doesn't fly here.

•       Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

•       Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

•       The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

•       The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

•       The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

•       The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?